The present invention generally relates to circuits, and more particularly, to a circuit and method for reducing parasitic bipolar effects during electrostatic discharges.
An integrated circuit or semiconductor device can be damaged when subjected to a voltage that is higher than the design voltage of the integrated circuit. Electrostatic discharge (xe2x80x9cESDxe2x80x9d), originating from such sources as a mechanical chip carrier, a plastic chip storage device, or even a human being can generate a voltage that is many times greater than the design voltage of the integrated circuit. For example, the typical human body can supply an electrostatic discharge in excess of 4 kilovolts. For integrated circuits that operate at voltages of less than, for example, 5 volts, an electrostatic discharge of such proportions can be devastating.
In order to protect the internal circuitry from electrical overstress (EOS), or ESD, events, protection circuits are utilized, generally between the internal circuitry and the input/output (xe2x80x9cI/Oxe2x80x9d) pins of the integrated circuit. One mechanism that can cause circuit failures during ESD events is a phenomenon known as xe2x80x9cbipolar snapbackxe2x80x9d.